US 2010/0059825 A1 · Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region

Abstract

A method of forming an integrated circuit 68 provides over a diffusion region 28 on a substrate 26 a gate electrode 36. A source electrode is provided by a source local interconnect conductor 30 and a drain electrode is provided by a drain local interconnect conductor 32. An insulator layer 38 is formed over these electrodes and respective electrode openings are formed through the insulator layer 38 so as to provide electrical connection to a Metal1 layer 46, 48, 50. The etching process for the electrode openings is controlled such that the maximum etching depth is insufficient to penetrate through the insulating layer 38 and accordingly short circuit a gate insulator layer 34 provided between the diffusion region 28 and the gate electrode 36. Thus, the gate opening may be positioned over the diffusion region 28. Double patterning followed by separate etching steps for the gate opening and the source/drain opening may be used to control the gate opening depth and permit the gate contact to be position overlying the diffusion region.

Claims50

Dependent claims

A method of making an integrated circuit, said method comprising the steps of:

forming on a diffusion region of a semiconductor substrate a gate electrode spaced by a gate insulator layer from said diffusion region and at least one local interconnect conductor, each local interconnect conductor respectively forming one of a source electrode and a drain electrode and said at least one local interconnect conductor extending above the diffusion region a distance comparable to a distance said gate electrode extends above the diffusion region;
depositing an upper insulator layer over said diffusion region, said gate electrode and said at least one local interconnect conductor;
etching through said upper insulator layer (a) at least one electrode opening, said opening reaching an upper surface of said at least one local interconnect conductors and (b) a gate opening overlying said diffusion region and reaching at least an upper surface of said gate electrode, etching of said gate opening being such that said gate opening has a maximum depth insufficient to reach said diffusion region;
and
depositing an electrode connection conductor in each of said openings.

2 more elements

Dependencies are inferred from the claim text.

Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region

Life of this patent

Integrated circuit and a method of making an integrated circuit to provide a gate contact over a diffusion region

Life of this patent

Abstract

Claims50