US 2010/0059810 A1Published application

Semiconductor device and a method of manufacturing the same

AssigneeRenesas Technology Corp.

InventorsTakuro HOMMA, Yasushi Ishii, Kota Funayama

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Abstract

The present invention can realize a highly-integrated semiconductor device having a MONOS type nonvolatile memory cell equipped with a split gate structure without deteriorating the reliability of the device. A memory gate electrode of a memory nMIS has a height greater by from 20 to 100 nm than that of a select gate electrode of a select nMIS so that the width of a sidewall formed over one (side surface on the side of a source region) of the side surfaces of the memory gate electrode is adjusted to a width necessary for achieving desired disturb characteristics. In addition, a gate electrode of a peripheral second nMIS has a height not greater than the height of a select gate electrode of a select nMIS to reduce the width of a sidewall formed over the side surface of the gate electrode of the peripheral second nMIS so that a shared contact hole is prevented from being filled with the sidewall.

Claims27

Dependent claims

A semiconductor device comprising:

a nonvolatile memory cell equipped with a first field effect transistor in a first region of a memory region and a second field effect transistor adjacent to the first field effect transistor in a second region of the memory region over a main surface of a semiconductor substrate;
and a third field effect transistor in a peripheral circuit region over the main surface of the semiconductor substrate,
the semiconductor device comprising:
a first insulating film formed in the first region;
a first gate electrode of the first field effect transistor formed in the first region via the first insulating film;
a second insulating film formed in the second region and having a charge storage layer having a charge storage function, and
a second gate electrode of the second field effect transistor formed in the second region via the second insulating film,
wherein the height of the first gate electrode from the main surface of the semiconductor substrate is lower than the height of the second gate electrode from the main surface of the semiconductor substrate, and
wherein the height of the third gate electrode of the third field effect transistor from the main surface of the semiconductor substrate is equal to or lower than the height of the first gate electrode from the main surface of the semiconductor substrate.

6 more elements

A method of manufacturing a semiconductor device comprising:

a nonvolatile memory cell equipped with a first field effect transistor in a first region of a memory region and a second field effect transistor adjacent to the first field effect transistor in a second region over a main surface of a semiconductor substrate;
and a third field effect transistor in a peripheral circuit region over the main surface of the semiconductor substrate, the method comprising the steps of:
(a) forming a first insulating film over the main surface of the semiconductor substrate in the first region and the peripheral circuit region;
(b) depositing a first conductor film and a third insulating film successively over the first insulating film;
(c) etching the third insulating film and the first conductor film in the memory region successively to form, in the first region via the first insulating film, a first gate electrode of the first field effect transistor having the first conductor film;
(d) after the step (c) above, forming a second insulating film including a charge storage layer having a charge storage function over the main surface of the semiconductor substrate;
(e) depositing a second conductor film over the second insulating film;
(f) anisotropically etching the second conductor film to form, in the second region via the second insulating film, a second gate electrode of the second field effect transistor having the second conductor film;
(g) removing the third insulating film;
(h) etching the first conductor film in the peripheral circuit region to form, in the peripheral circuit region via the first insulating film, a third gate electrode of the third field effect transistor having the first conductor film;
(i) after the step (h) above, depositing a fourth insulating film over the main surface of the semiconductor substrate;
and
(j) etching the fourth insulating film to form sidewalls over the side surfaces of the first gate electrode, the second gate electrode, and the third gate electrode.

10 more elements

A method of manufacturing a semiconductor device comprising:

a nonvolatile memory cell equipped with a first field effect transistor in a first region of a memory region and a second field effect transistor adjacent to the first field effect transistor in a second region over a main surface of a semiconductor substrate;
and a third field effect transistor in a peripheral circuit region over the main surface of the semiconductor substrate, the method comprising the steps of:
(a) forming a first insulating film over the main surface of the semiconductor substrate in the first region and the peripheral circuit region;
(b) depositing a first conductor film and a third insulating film successively over the first insulating film;
(c) etching the third insulating film and the first conductor film in the memory region successively to form, in the first region via the first insulating film, a first gate electrode of the first field effect transistor having the first conductor film;
(d) after the step (c) above, forming a second insulating film including a charge storage layer having a charge storage function over the main surface of the semiconductor substrate;
(e) depositing a second conductor film over the second insulating film;
(f) anisotropically etching the second conductor film to form, in the second region via the second insulating film, a second gate electrode of the second field effect transistor having the second conductor film;
(g) removing the third insulating film placed over the upper surface of the first conductor film of the peripheral circuit region;
(h) etching the first conductor film in the peripheral circuit region to form, in the peripheral circuit region via the first insulating film, a third gate electrode of the third field effect transistor having the first conductor film;
(i) after the step (h) above, depositing a fourth insulating film over the main surface of the semiconductor substrate;
and
(j) etching the fourth insulating film to form sidewalls over the side surfaces of the first gate electrode, the second gate electrode, and the third gate electrode.

10 more elements

Dependencies are inferred from the claim text.