Method and system for mounting circuit design on reconfigurable device

A method of generating configuration data for reconfiguring a reconfigurable device,

• wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix,
• the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and
• the method comprises:
• preparing hardware information on a computer accessible database, the hardware information including definition data for the plurality of processing elements included in respective groups and definition data for the routing matrix;
• and
• mapping a circuit design onto the plurality of processing elements for implementing the circuit design in the device by the configuration data, by having the computer carry out an iterative algorithm that minimizes a cost function,
• wherein the cost function includes an item that minimizes usage of the second-level routing matrix.

A method that includes mapping a circuit design onto a reconfigurable device,

• wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix,
• the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and
• the circuit design includes a data flow graph in which functions to be implemented in the device are expressed as a plurality of functional blocks that are capable of being implemented in processing elements out of the plurality of processing elements and connections between the plurality of functional blocks,
• the mapping comprising:
• provisionally assigning the plurality of functional blocks to processing elements out of the plurality of processing elements divided into the plurality of groups;
• and
• changing assignments of the functional blocks to the plurality of processing elements using an iterative algorithm that minimizes a cost function;
• wherein the cost function includes an item that minimizes usage of the second-level routing matrix, and changing the assignments includes finding a value of the cost function from connections between a plurality of processing elements to which the plurality of functional blocks have been assigned.

A program for causing a computer to generate configuration data for configuring a reconfigurable device,

• wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix,
• the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and
• the program comprises:
• preparing hardware information on a computer accessible data base, the hardware information including definition data for the plurality of processing elements included in the respective groups and definition data for the routing matrix;
• and
• mapping a circuit design onto the plurality of processing elements for implementing the circuit design in the device by the configuration data, by having the computer carry out an iterative algorithm that minimizes a cost function,
• wherein the cost function includes an item that minimizes usage of the second-level routing matrix.

A program for causing a computer to map a circuit design onto a reconfigurable device,

• wherein the device includes a plurality of processing elements and a routing matrix for connecting the plurality of processing elements and is reconfigured by changing functions of respective processing elements in the plurality of processing elements and/or changing at least some connections of the routing matrix,
• the plurality of processing elements are divided into a plurality of groups, processing elements included in each group are connected in a range of a first delay by a first-level routing matrix included in the routing matrix, and processing elements included in different groups are connected with a different delay to the first delay via a second-level routing matrix included in the routing matrix, and
• the circuit design includes a data flow graph in which functions to be implemented in the device are expressed as a plurality of functional blocks that are capable of being implemented in processing elements out of the plurality of processing elements and connections between the plurality of functional blocks,
• the program comprising:
• provisionally assigning the plurality of functional blocks to processing elements out of the plurality of processing elements divided into the plurality of groups;
• and
• changing assignments of the functional blocks to the plurality of processing elements using an iterative algorithm that minimizes a cost function,
• wherein the cost function includes an item that minimizes usage of the second-level routing matrix, and the changing of the assignments includes finding a value of the cost function from connections between a plurality of assigned processing elements to which the plurality of functional blocks have been assigned.