Method and System for Testing an Electronic Circuit to Identify Multiple Defects

A system, comprising:

• a test engine coupled to a device under test (DUT), the DUT comprising a plurality of test stumps;
• the test engine configured to:
• generate a plurality of test patterns arranged in an order, wherein each test pattern is associated with an associated circuit input state, and each test pattern causes an associated output of the DUT;
• and
• apply to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to a first log interval after the first test pattern, thereby generating a first associated output;
• a trace array coupled to the DUT and configured to:
• store a plurality of known outputs, wherein the plurality of known outputs comprises a known output associated with each test pattern as applied to an electronic circuit configured similar to the DUT and functioning in a known state;
• a controller coupled to the test engine and the trace array and configured to compare the first associated output with a first known output of the plurality of known outputs, wherein the first known output is associated with the same test pattern as the first associated output;
• and
• the test engine further configured to:
• in the event the first associated output matches the first known output, proceed with additional test procedures;
• and
• in the event the first associated output does not match the first known output:
• store indicia of the first mismatch;
• cause the electronic circuit to appear to assume the first known output state;
• and
• proceed with additional test procedures.

A processor comprising a computer program product for testing an electronic circuit, the computer program product having a tangible computer-readable medium with a computer program embodied thereon, the computer program comprising:

• computer code for selecting a plurality of test patterns arranged in an order, wherein each test pattern is associated with an associated circuit input state, and each test pattern causes an associated output of an electronic circuit;
• computer code for selecting a first log interval;
• computer code for storing a plurality of known outputs, wherein the plurality of known outputs comprises a known output associated with each test pattern as applied to an electronic circuit functioning in a known state;
• computer code for testing an electronic circuit in a first test by applying to the electronic circuit a first subset range of the plurality of test patterns sequentially in the order, from a first test pattern to the first log interval after the first test pattern, thereby generating a first associated output;
• computer code for comparing the first associated output with a first known output of the plurality of known outputs, wherein the first known output is associated with the same test pattern as the first associated output;
• computer code for, in the event the first associated output matches the first known output, proceeding with additional test procedures;
• and
• computer code for, in the event the first associated output does not match the first known output:
• storing indicia of the first mismatch;
• causing the electronic circuit to appear to assume the first known output state;
• and
• proceeding with additional test procedures.