Dynamic Merging of Pipeline Stages in an Execution Pipeline to Reduce Power Consumption

A method of executing instructions in an execution unit of the type including an execution pipeline with a plurality of pipeline stages, wherein the plurality of pipeline stages includes a first pipeline stage and a second pipeline stage, wherein the first pipeline stage includes a first latch and first execution logic coupled to an output of the first latch and configured to process input data stored in the first latch, and the second pipeline stage includes a second latch and second execution logic coupled to an output of the second latch and configured to process input data stored in the second latch, and wherein the second latch is coupled intermediate to the first and second execution logic to latch output data from the first execution logic for use as input data by the second execution logic, the method comprising:

• operating the execution pipeline in a first mode by clocking the first and second latches such that the first and second pipeline stages perform steps for separate instructions in each clock cycle;
• and
• operating the execution pipeline in a second mode by setting the second latch to a transparent state to merge the first and second execution logic together such that the first and second pipeline stages perform steps for the same instruction in each clock cycle.

A method of executing instructions in an execution unit of the type including an execution pipeline with a plurality of pipeline stages, wherein each pipeline stage includes a latch and execution logic coupled to an output of such latch and configured to process input data stored in such latch, the method comprising:

• in a first mode, clocking the latches in each of the plurality of pipeline stages at a first clock frequency such that the plurality of pipeline stages perform steps for separate instructions in each clock cycle;
• and
• in a second mode, clocking the latches in a first subset of the plurality of pipeline stages at a second clock frequency that is lower than the first clock frequency, and setting the latches in a second subset of the plurality of pipeline stages to a transparent state such that, for each pipeline stage in the second subset of pipeline stages, the execution logic of such pipeline stage is merged with the execution logic of an immediately preceding pipeline stage among the plurality of pipeline stages so that such pipeline stage and immediately preceding pipeline stage perform steps for the same instruction in each clock cycle.