Semiconductor memory devices and methods of arranging memory cell arrays thereof

Abstract

A semiconductor memory device and a method of arranging a memory cell array of the semiconductor device are provided. The semiconductor memory device has a memory cell array including a word line pair including a first word line and a second word line that are arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction. The first word line and the second word line are simultaneously activated. Therefore, disturbance that may be generated between adjacent memory cells in the semiconductor memory cell can be prevented, integration density of the semiconductor memory device can be enhanced, and the number of word lines to be driven may be reduced to employ a sub-word line structure.

Dependencies are inferred from the claim text.