Front-end sampling technique for analog-to-digital converters
AssigneeAnalog Devices, Inc.
InventorsMichael ELLIOTT, Frank MURDEN
Life of this patent
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Abstract
Embodiments of the present invention provide a pipeline ADC front-end sampling structure that provides a continuous time input signal to a flash comparator for sampling. By providing a continuous time input signal to the flash comparator, no delay is introduced from the need to transfer a DC charge representing the sampled input to the flash comparator. Matching sampling networks in the residual generator and the flash comparator are avoided due to the high bandwidth response requirements of the residual generator and the flash comparator when operating on high frequency input signals.
Claims19
In a pipeline analog-to-digital converter (ADC), a front-end ADC stage comprising:
- a multiplying digital-to-analog converter (MDAC), the MDAC comprising:
- a first differential input;
- a second differential input;
- a first switch coupled between the first and second differential inputs;
- a first input capacitor coupled to the first switch and a first differential component of an analog input signal;
- and
- a second input capacitor coupled to the first switch and a second differential component of the analog input signal;
- and
- a flash comparator, the flash comparator comprising:
- a third differential input;
- a fourth differential input;
- a second switch coupled between the third and fourth differential inputs;
- a third input capacitor coupled to the second switch and the first differential component of the analog input signal;
- a fourth input capacitor coupled to the second switch and the second differential component of the analog input signal;
- a third switch coupled to a first reference voltage and the third input capacitor;
- and
- a fourth switch coupled to a second reference voltage and the fourth input capacitor, wherein an output of the flash comparator is coupled to the MDAC.
In a pipeline analog-to-digital converter (ADC), a method for sampling an analog input signal within a front-end ADC stage, comprising:
- during a first phase:
- activating a first switch coupled between a first differential input and a second differential input of a flash comparator;
- activating a second switch coupled between a first reference voltage and the first differential input of the flash comparator to charge a first input capacitor coupled between the second switch and the first differential input of the flash comparator to the first reference voltage;
- and
- activating a third switch coupled between a second reference voltage and the second differential input of the flash comparator to charge a second input capacitor coupled between the third switch and the second differential input of the flash comparator to the second reference voltage;
- during a second phase:
- deactivating the first, second and third switches;
- activating a fourth switch coupled between a first differential input and a second differential input of a multiplying digital-to-analog converter (MDAC);
- and
- providing a differential analog input signal as a continuous time signal to the differential inputs of the flash comparator.
In a pipeline analog-to-digital converter (ADC), a method for sampling an analog input signal within a front-end ADC stage, comprising
- precharging reference capacitors of a flash comparator during a first phase;
- sampling a differential analog input signal using a sampling network coupled to a differential input of a multiplying digital-to-analog converter (MDAC) during a second phase;
- and
- sampling the differential analog input signal as a continuous time signal at regeneration nodes inside the flash comparator during the second phase.
In a pipelined analog-to-digital converter (ADC), a front-end ADC stage comprising:
- an MDAC having a first differential input and a second differential input;
- a first pair of sampling capacitors, a first sampling capacitor coupled to the first differential input and a second sampling capacitor coupled to a second differential input;
- a flash comparator having a third differential input and a fourth differential input;
- a second pair of sampling capacitors, a third sampling capacitor coupled to the third differential input and a fourth sampling capacitor coupled to the fourth differential input;
- first switch control, alternatively coupling the third sampling capacitor between a first reference voltage and a first component of a differential analog input signal and alternatively coupling the fourth sampling capacitor between a second reference voltage and a second component of the differential analog input signal;
- and
- second switch control, alternatively coupling and decoupling the first and second sampling capacitors to the differential analog input signal,
- wherein:
- the first pair of sampling capacitors are decoupled from the differential analog input signal when the second pair of sampling capacitors are coupled to the first and second reference voltages;
- and
- the first pair of sampling capacitors are coupled to the differential analog input signal when the second pair of sampling capacitors are coupled to the differential analog input signal.
Dependencies are inferred from the claim text.