Apparatus and Methods for Adjusting Performance of Integrated Circuits

A method of using a programmable logic device (PLD) to implement an electronic circuit, the method comprising:

• mapping the electronic circuit to functional resources within the programmable logic device (PLD) to generate a design;
• deriving a body-bias value from a delay representative of a signal propagation delay within at least one portion of the generated design;
• and
• programming a body-bias level of at least one transistor within the at least one portion of the generated design to the body-bias value.

A method of realizing a user's circuit in at least one circuit region in a programmable logic circuit (PLD), the method comprising:

• selecting a body-bias level for at least one transistor in the circuit region;
• generating an initial placement of the circuit region within the programmable logic device (PLD);
• and
• changing at least once the body-bias level to be applied to the at least one transistor in the circuit region to another level if the existing body-bias level and placement fail to meet prescribed performance criteria.