Dual Stress Liner Device and Method
AssigneeToshiba America Electronic Components, Inc.
InventorGaku SUDO
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Abstract
A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
Claims7
A semiconductor device, comprising:
- a substrate;
- first and second field-effect transistors formed on and in said substrate;
- a tensile stress liner formed over the first field-effect transistor;
- a compression stress liner formed over the second field-effect transistor;
- and
- a conductive contact disposed between the first and second field-effect transistors, wherein a first side of said contact is adjacent to said tensile stress liner, an opposite second side of said contact is adjacent to said compression stress liner, and wherein said stress liners do not overlap.
Dependencies are inferred from the claim text.