Semiconductor Device with Crack Prevention Ring
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPing-Wei Wang, Chii-Ming Morris Wu
Life of this patent
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Abstract
A crack prevention ring at the exterior edge of an integrated circuit prevents delamination and cracking during the separation of the integrated circuits into individual die. The crack prevention ring extends vertically into a semiconductor workpiece to at least a metallization layer of the integrated circuit. The crack prevention ring may be formed simultaneously with the formation of test pads of the integrated circuits. The crack prevention ring may be partially or completely filled with conductive material. An air pocket may be formed within the crack prevention ring beneath a passivation layer of the integrated circuit. The crack prevention ring may be removed during the singulation process.
Claims19
A semiconductor device comprising:
- an integrated circuit;
- a plurality of metallization layers, the plurality of metallization layers comprising a first metallization layer and at least one second metallization layer disposed over the first metallization layer, wherein each metallization layer is formed in an insulating layer;
- a scribe line adjacent the integrated circuit;
- a seal ring substantially surrounding the integrated circuit;
- and
- a crack prevention ring disposed around an exterior edge of the integrated circuit, the crack prevention ring being interjacent the seal ring and the scribe line and comprising a trench completely filled with a conductive material and extending into a plurality of non-conductive layers at least to a depth of the at least one second metallization layer.
The semiconductor device according to claim 12, wherein the at least one low-k dielectric layer comprises a chemical vapor deposition (CVD) dielectric layer, SiOC, SiOCN, spin-on SiOC, a CVD polymer, a spin-on polymer, fluorinated silicate glass (FSG), SiO2, or combinations thereof.
A semiconductor device comprising:
- a semiconductor wafer;
- a plurality of integrated circuits formed on the semiconductor wafer;
- a series of scribe lines interjacent and separating respective ones of the plurality of integrated circuits;
- at least one of said plurality of integrated circuits including:
- a first metallization layer extending a first depth from a top surface of the integrated circuit, and at least one second metallization layer disposed over the first metallization layer and extending a second depth from the top surface of the integrated circuit;
- a seal ring formed around a periphery of the at least one integrated circuit;
- and
- a crack prevention ring formed in a trench along the periphery of the at least one integrated circuit, wherein the trench is located between the seal ring and the adjacent scribe line, and wherein the trench extends at least to the second depth of the at least one second metallization layer, and wherein the trench is completely filled a conductive material.
Dependencies are inferred from the claim text.