Semiconductor integrated circuit including transistor having diffusion layer formed at outside of element isolation region for preventing soft error

A semiconductor integrated circuit device, comprising:

• an MISFET comprising a drain diffusion layer of a first conductivity type, a source diffusion layer of the first conductivity type, a gate electrode, and a second substrate/well of a second conductivity type, the second conductivity type being an opposite of the first conductivity type, the drain diffusion layer having a rectangular shape;
• a first diffusion layer of the first conductivity type provided so as to face three sides other than a side in a direction of the source diffusion layer with an isolation therebetween respectively;
• and
• a second diffusion layer of the second conductivity type provided so as to be adjacent to the source diffusion layer or so as to come in contact with the source diffusion layer.

A semiconductor integrated circuit device, comprising:

• a gate electrode of at least either a P-channel MISFET or an N-channel MISFET provided in a direction parallel to a direction of a well isolation boundary phase between the P-channel MISFET and the N-channel MISFET;
• a first diffusion layer having a same conductivity type as that of a drain diffusion layer of one of the MISFETs provided in two regions with the drain diffusion layer of the MISFET therebetween through an isolation respectively in a direction orthogonal to the gate electrode;
• and
• a second diffusion layer having a conductivity type different from that of the drain diffusion layer of one of the MISFETs provided between the well isolation boundary phase and one of a source diffusion layer or the drain diffusion layer of one of the MISFETs through an isolation, respectively.