Semiconductor Device and Method of Fabricating the same
AssigneeHynix Semiconductor Inc.
InventorKwang Seok JEON
Life of this patent
Estimating the term…
Abstract
A semiconductor device and a method of fabricating the same. In accordance with a method of fabricating a semiconductor device according to an aspect of the invention, a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer are sequentially stacked over a semiconductor substrate. The gate electrode layer and the second conductive layer are patterned. A first passivation layer is formed on sidewalls of the gate electrode layer. Gate patterns are formed by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed. A second passivation layer is formed on the entire surface along a surface of the gate patterns including the first passivation layer.
Claims42
A semiconductor device, comprising:
- gate patterns each comprising a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, and a gate electrode layer sequentially stacked over a semiconductor substrate, the gate electrode layer defining sidewalls;
- a first passivation layer formed on the sidewalls of the gate electrode layer;
- and
- a second passivation layer formed on the entire surface along a surface of the first passivation layer and the gate patterns.
A semiconductor device, comprising:
- gate patterns each comprising a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, and a gate electrode layer sequentially stacked over a semiconductor substrate, the gate electrode layer defining sidewalls;
- a first passivation layer formed on the sidewalls of the gate electrode layer;
- and
- a second passivation layer formed on a surface of the first passivation layer and over the gate patterns.
A method of fabricating a semiconductor device, comprising:
- sequentially stacking a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer over a semiconductor substrate, the gate electrode layer defining sidewalls;
- patterning the gate electrode layer and the second conductive layer;
- forming a first passivation layer on the sidewalls of the gate electrode layer;
- forming gate patterns by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed;
- and
- forming a second passivation layer on the entire surface along a surface of the gate patterns including the first passivation layer.
A method of fabricating a semiconductor device, comprising:
- sequentially stacking a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer over a semiconductor substrate, the gate electrode layer defining sidewalls;
- patterning the gate electrode layer and the second conductive layer;
- forming a first passivation layer on the sidewalls of the gate electrode layer;
- forming a second passivation layer on the entire surface including the first passivation layer;
- and
- forming gate patterns by etching the second passivation layer formed over the dielectric layer, the dielectric layer, the first conductive layer, and the tunnel dielectric layer.
A method of fabricating a semiconductor device, comprising:
- sequentially stacking a tunnel dielectric layer, a first conductive layer, a dielectric layer, a second conductive layer, and a gate electrode layer over a semiconductor substrate, the gate electrode layer defining sidewalls;
- patterning the gate electrode layer and the second conductive layer;
- forming a first passivation layer on sidewalls of the gate electrode layer;
- forming gate patterns by etching the dielectric layer, the first conductive layer, and the tunnel dielectric layer, which have been exposed;
- and
- forming second and third passivation layers on the entire surface along a surface of the gate patterns including the first passivation layer.
Dependencies are inferred from the claim text.