Semiconductor device having tri-gate structure and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorsTakashi IZUMIDA, Takahisa Kanemura, Nobutoshi Aoki
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Abstract
A semiconductor device of an example of the invention comprises a memory cell and a select gate transistor provided for the memory cell. A gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
Claims18
A semiconductor device comprising:
- a memory cell;
- and
- a select gate transistor provided for the memory cell;
- wherein a gate electrode of the select gate transistor has a Tri-gate structure in which an upper surface of a gate insulating film formed above a channel of the select gate transistor is set higher than a portion of an upper surface of an element isolation region of the select gate transistor.
A manufacturing method of a semiconductor device having a select gate transistor having a Tri-gate structure, comprising:
- forming a first element isolation region and first semiconductor region in a select gate formation region of a substrate and forming a second element isolation region and second semiconductor region in a word line formation region of the substrate;
- sequentially forming a tunnel insulating film, charge storage layer and block film in the select gate formation region and in the word line formation region;
- removing the tunnel insulating film, charge storage layer and block film in the select gate formation region and removing an insulating film in the first element isolation region to set an upper surface of the first semiconductor region higher than an upper surface of the first element isolation region;
- forming the gate insulating layer of the select gate transistor above the first semiconductor region to set an upper surface of the gate insulating layer of the select gate transistor higher than the upper surface of the first element isolation region;
- and
- depositing a gate electrode layer in the select gate formation region and in the word line formation region.
A manufacturing method of a semiconductor device having a select gate transistor having a Tri-gate structure, comprising:
- forming a first element isolation region and first semiconductor region in a select gate formation region of a substrate and forming a second element isolation region and second semiconductor region in a word line formation region of the substrate;
- sequentially forming a gate insulating film and floating gate electrode layer in the first and second semiconductor regions;
- depositing an inter electrode insulating film in the select gate formation region and in the word line formation region;
- removing a portion of the inter electrode insulating film in the select gate formation region, recessing a portion of the first element isolation region in the select gate formation region that does not contact the first semiconductor region and forming a projecting portion whose upper surface is set higher than an upper surface of the gate insulating film and that contacts a side surface of the semiconductor region;
- and
- depositing a control gate electrode layer in the select gate formation region and in the word line formation region.
Dependencies are inferred from the claim text.