High shrinkage stress silicon nitride (SiN) layer for NFET improvement

A semiconductor substrate having one or more field effect transistors (FETs), the substrate comprising:

• a first n-type FET having a source region, a drain region and a gate structure;
• and
• a stressed film overlying the source region, the drain region and the gate structure, the stressed film imparting a tensile stress of at least about 1.7 Gpa within a channel region extending between the source region and the drain region.

A method of forming a stressed layer for generating tensile stress within a channel region of a field-effect transistor (FET) in a semiconductor structure, the method comprising:

• spinning on a dielectric material over a gate structure, a source region and a drain region of a FET;
• heating the dielectric material to form a dielectric film, and
• curing the dielectric film to shrink the dielectric film thereby forming the stressed layer.