Segmenting Integrated Circuit Layout Design Files Using Speculative Parsing

A method of parsing integrated circuit layout design data, comprising:

• (a) identifying data in integrated circuit layout design data matching a cell record start value;
• (b) parsing data in the integrated circuit layout design data subsequent to the identified data, until a threshold amount of subsequent data has been parsed without identifying another cell record start value;
• and
• (c) when the threshold amount of subsequent data has been parsed without identifying another cell record start value, designating the next data in the integrated circuit layout design data matching a cell record start value as a segment boundary;
• (d) repeating steps (a)-(c) until the integrated circuit layout design data has been divided into segments by segment boundaries;
• and
• (e) providing the segments to a parallel processing computing system for parsing in parallel.

A method, comprising:

• (a) selecting a segment of data in integrated circuit layout design data;
• (b) from a location before a middle of the identified segment, identifying data in the segment matching a cell record start value;
• (c) parsing data in the integrated circuit layout design data subsequent to the identified data, until a threshold amount of subsequent data has been parsed without identifying another cell record start value;
• and
• (e) when the threshold amount of subsequent data has been parsed without identifying another cell record start value, designating the next data in the integrated circuit layout design data matching a cell record start value as a segment boundary dividing the selected segment into two smaller segments;
• (f) repeating steps (a)-(e);
• and
• (g) providing the segments to a parallel processing computing system for parsing in parallel.