Circuit analysis method, semiconductor integrated circuit manufacturing method, circuit analysis program and circuit analyzer

Abstract

To perform a timing analysis at a high analysis accuracy while reducing a TAT. A circuit analyzer according to the present invention performs a timing analysis on a design target circuit after a layout change. The circuit analyzer includes a storage device in which an extraction range reference is set, an extraction range setting unit and a timing analysis unit. The extraction setting unit sets the extraction range reference including a layout-changed portion, as a parasitic element extraction target range. The timing analysis unit performs a timing analysis by using, as an analysis target, a predetermined range including a parasitic element extracted from the extraction target range.

Dependencies are inferred from the claim text.