Dummy metal insertion processing method and apparatus
AssigneeFujitsu Limited
InventorIzumi Nitta
Life of this patent
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Abstract
A method includes: before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data while changing an origin position of the dummy pattern template to optimize the origin position of the dummy pattern template; and upon detecting that the result of the timing verification processing has no problem, superposing and arranging the dummy pattern template onto the layout area at the origin position of the dummy pattern template, to generate the layout data after inserting the dummy metal.
Claims10
A computer-readable storage medium storing a dummy metal insertion processing program for causing a computer to execute a process comprising:
- before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data of said semiconductor circuit, while changing an origin position of said dummy pattern template, to optimize said origin position of said dummy pattern template;
- and
- upon detecting that it is confirmed that a result of said timing verification processing has no problem, superposing and arranging said dummy pattern template onto said layout area defined by said layout data at the optimized origin position of said dummy pattern template, to generate second layout data after inserting said dummy metal.
A dummy metal insertion processing method, comprising:
- before carrying out a timing verification processing of a semiconductor circuit, preliminarily superposing and arranging a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by layout data of said semiconductor circuit, while changing an origin position of said dummy pattern template, to optimize said origin position of said dummy pattern template;
- and
- upon detecting that it is confirmed that a result of said timing verification processing has no problem, superposing and arranging said dummy pattern template onto said layout area defined by said layout data at the optimized origin position of said dummy pattern template, to generate second layout data after inserting said dummy metal.
A dummy metal insertion processing apparatus, comprising:
- a layout data storage device storing layout data of a semiconductor circuit;
- a unit that preliminarily superposes and arranges, before carrying out a timing verification processing of said semiconductor circuit, a dummy pattern template representing an arrangement pattern of dummy metal, onto a layout area defined by said layout data stored in said layout data storage device, while changing an origin position of said dummy pattern template, to optimize said origin position of said dummy pattern template;
- and
- a unit that superposes and arranges, upon detecting that it is confirmed that a result of said timing verification processing has no problem, said dummy pattern template onto said layout area defined by said layout data at the optimized origin position of said dummy pattern template, to generate second layout data after inserting said dummy metal.
Dependencies are inferred from the claim text.