Operation timing verifying apparatus and program

An operation timing verifying program for making a computer to function as means to read in circuit data representing a circuit layout including a plurality of delay elements and to perform an operation timing analysis in a settable operating condition on said circuit layout, said verifying program comprising:

• an operation-violating circuit path extracting process that sets an unreal corner condition that all of said delay elements present a maximum delay as said operating condition and performs said operation timing analysis, thereby extracting an operation-violating circuit path, if any, from said circuit layout;
• and
• an operation violation determining process that, if said operation-violating circuit path is extracted, sets a real corner condition that at least one element type of delay elements from among said delay elements present a maximum delay as said operating condition and performs said operation timing analysis on only said operation-violating circuit path to determine again whether an operation violation exists therein.

An operation timing verifying method for making a computer to function as means to read in circuit data representing a circuit layout including a plurality of delay elements and to perform an operation timing analysis in a settable operating condition on said circuit layout, said operation timing verifying method comprising;

• extracting an operation-violating circuit path, if any, from said circuit layout by setting an unreal corner condition that all of said delay elements present a maximum delay as said operating condition and performing said operation timing analysis;
• and
• determining an operation violation determining, if said operation-violating circuit path is extracted, by setting a real corner condition that at least one element type of delay elements from among said delay elements present a maximum delay as said operating condition and performing said operation timing analysis on only said operation-violating circuit path to determine again whether an operation violation exists therein.

A system for verifying an operation timing comprising a computer and an operation verifying program for making the computer to function as means to read in circuit data representing a circuit layout including a plurality of delay elements and to perform an operation timing analysis in a settable operating condition on said circuit layout, said operation timing verifying program comprising:

• extracting an operation-violating circuit path, if any, from said circuit layout by setting an unreal corner condition that all of said delay elements present a maximum delay as said operating condition and performing said operation timing analysis;
• and
• determining an operation violation determining, if said operation-violating circuit path is extracted, by setting a real corner condition that at least one element type of delay elements from among said delay elements present a maximum delay as said operating condition and performing said operation timing analysis on only said operation-violating circuit path to determine again whether an operation violation exists therein.

An operation timing verifying program product comprising a operation timing verifying program for making a computer to function as means to read in circuit data representing a circuit layout including a plurality of delay elements and to perform an operation timing analysis in a settable operating condition on said circuit layout, said operation timing verifying program comprising:

• extracting an operation-violating circuit path, if any, from said circuit layout by setting an unreal corner condition that all of said delay elements present a maximum delay as said operating condition and performing said operation timing analysis;
• and
• determining an operation violation determining, if said operation-violating circuit path is extracted, by setting a real corner condition that at least one element type of delay elements from among said delay elements present a maximum delay as said operating condition and performing said operation timing analysis on only said operation-violating circuit path to determine again whether an operation violation exists therein.