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AssigneeKyoto University
InventorsHajime Shimada, Shinobu Miwa, Shinji Tomita
Estimating the term…
In a microprocessor for pipeline processing instruction execution, dependency relationship information representing a dependency relationship of each of a plurality of instructions with all the preceding instructions is stored, and whether or not the instructions in stages after instruction issue depend on the instruction of a miss speculation is judged based on the dependency relationship information if the miss speculation occurs during the execution of the plurality of instructions in accordance with a set schedule. Thus, this microprocessor can perform a recovery processing for invalidating only the instructions in a dependency relationship at once in the case of a miss speculation in speculative scheduling.
A microprocessor for pipeline processing instruction execution, comprising:
A method for encoding a bit vector, the method being used for a microprocessor for pipeline processing the execution of instructions and the bit vector indicating a dependency relationship with all the instructions preceding the instruction, wherein the bit vector is comprised of a bit string indicating whether or not each bit is in a dependency relationship with an instruction of an entry number of an instruction window unit corresponding to the bit number of this bit.
A method for generating a bit vector, the method being used for a microprocessor for pipeline processing the execution of instructions and the bit vector indicating a dependency relationship with all the instructions preceding the instruction and comprised of a bit string indicating whether or not each bit is in a dependency relationship with an instruction of an entry number of an instruction window unit corresponding to the bit number of this bit, wherein the bit vector is generated by taking a logical sum of the bit vectors of the instructions in a dependency relationship with the instruction of this bit vector.
Dependencies are inferred from the claim text.