Selectively performing a single cycle write operation with ecc in a data processing system

A circuit, comprising:

• a memory having error correction and having parity, the memory comprising a plurality of memory banks;
• circuitry which requests a read operation having a first data size to a first address in the memory,
• wherein when parity is enabled, the read operation having the first data size to the first address in the memory comprises accessing only a first portion of the plurality of memory banks, and
• wherein when error correction is enabled, the read operation having the first data size to the first address in the memory comprises accessing both the first portion of the plurality of memory banks and a second portion of the plurality of memory banks.

A method, comprising:

• providing a memory having ECC error correction;
• providing circuitry for initiating a write operation to the memory,
• wherein the memory comprises a plurality of banks, wherein N is a width of the memory, M is a width of one of the plurality of banks in the memory, and N and M are integers,
• wherein when ECC error correction is enabled and the write operation has a size of less than N bits, the write operation comprises performing no read cycle to the memory for computing check bits, and
• wherein when ECC error correction is enabled and the write operation has the size of N bits and initialization of the memory is not being performed, the write operation comprises performing the read cycle for computing check bits.