Information processing apparatus and compiling method
AssigneeKabushiki Kaisha Toshiba
InventorsYoriharu Takai, Kenji Yoshida
Life of this patent
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AssigneeKabushiki Kaisha Toshiba
InventorsYoriharu Takai, Kenji Yoshida
Estimating the term…
According to one embodiment, an information processing apparatus includes a processor, a cache, and a cache controller. The processor is configured to output a memory access request for accessing an entity of a variable stored in a variable-storage region provided in a memory by using first or second memory address. Both the first and second memory addresses are allocated to the variable-storage region. The cache is configured to store some of data items stored in the memory. The cache controller is configured to access the memory or the cache by using a memory address designating the variable-storage region, in accordance with one of the first and second memory addresses which is included in a memory access request coming from the processor.
An information processing apparatus comprising:
An information processing system comprising:
A compile method of generating a program to be executed in an information processing apparatus configured to read and write in a cache-off mode where write access of a write-through scheme is allowed and reading data from a cache is prohibited when a memory address in a memory access request from a processor is a first memory address, and to read and write in a cache-on mode where write access of the write-back scheme is allowed and reading data from the cache is allowed when the memory address in the memory access request is the second memory address, the method comprising:
Dependencies are inferred from the claim text.