Transient Transactional Cache

A processor comprising:

• an execution core configured to execute instructions, wherein the execution core is configured to generate memory read and write operations responsive to instruction execution, and wherein the execution core is configured to generate transactional read and write operations responsive to executing transactional instructions;
• a level 1 (L1) data cache coupled to the execution core and configured to store data;
• and
• a transient/transactional cache coupled to the execution core, wherein the transient/transactional cache is configured to cache memory data accessed responsive to memory read and write operations to identify potentially transient data and to prevent the identified transient data from being stored in the L1 data cache, and wherein the transient/transactional cache is configured to cache transaction data accessed responsive to transactional read and write operations to track transactions, and wherein each entry in the transient/transactional cache is usable for transaction data and for transient data at different points in time.