Guaranteed memory card performance to end-of-life

A method for maintaining the performance of a memory system which includes a set of memory system configuration settings, a non-volatile memory, and an error detection and correction code (ECC) circuit, the method comprising:

• establishing a first latency threshold level and a second latency threshold level;
• associating a first set of operating parameters with the first latency threshold level and a second set of operating parameters with the second latency threshold level;
• collecting and storing in real-time a group of error correction statistics for the memory system according to predetermined memory transfer sizes;
• calculating a current latency level for using the group of error correction statistics;
• comparing, dynamically, the current latency level with the first latency threshold level and the second latency threshold level;
• and
• adjusting the set of memory system configuration settings based on the first set of operating parameters if the current latency level is greater than or equal to the first latency threshold, and adjusting the set of memory system configuration settings based on the second set of operating parameters if the current latency level is greater than or equal to the second latency threshold.

A method for maintaining the performance of a memory system which includes a system clock signal, a non-volatile memory, and an error detection and correction code (ECC) circuit, the method comprising:

• identifying a first number of errors detected and corrected by the ECC circuit for a memory transfer size specific to the usage of the memory system;
• identifying a second number of errors detected and corrected by the ECC circuit for the memory transfer size, at a time subsequent to when the first number of errors was identified;
• and
• increasing a clock signal frequency if the second number of errors is greater than the first number of errors.

A method for maintaining the performance of a memory system which includes a non-volatile memory, a first error detection and correction code (ECC) circuit, and a second ECC circuit, the method comprising:

• identifying a first number of errors detected and corrected by the first ECC circuit for a memory transfer size specific to the usage of the memory system;
• identifying a second number of errors detected and corrected by the first ECC circuit for the memory transfer size, at a time subsequent to when the first number of errors was identified;
• and
• enabling the second ECC circuit such that the first ECC circuit and the second ECC circuit operate in parallel if the second number of errors is greater than the first number of errors.