Lane merging

A method of merging data comprising:

• receiving an indication of which of a plurality of data lanes are active;
• selecting a repeating sequence of data lanes based on said indication;
• for each active data lane, receiving data words and timing said words through a buffer associated with said each active data lane;
• merging words onto a parallel bus from said each buffer in a pre-defined repeating sequence of data lanes.

A method of handling data comprising:

• receiving data words from a first parallel data bus;
• selecting at least two of a plurality of serial data lanes;
• distributing data words from said parallel bus to each selected data lane such that data words are distributed to each selected data lane in a repeating sequence of data lanes;
• timing data words from said each selected data lane through an associated buffer;
• merging data words from said associated buffer of said each selected data lane onto a second parallel bus such that data words from said each selected data lane are merged onto said second parallel bus in said repeating sequence of data lanes.

A receiver for merging data, comprising:

• a data lane controller for terminating each of a plurality of serial data lanes;
• a buffer associated with each said data lane controller;
• a lane merger associated with an output of each said buffer and for inputting a parallel data bus;
• a clock for timing any data words in any said buffer through said buffer;
• a receive controller operatively connected to each said data lane controller, each said buffer, and said lane merger for establishing at least one data lane of said plurality of serial data lanes as an active data lane and for passing data words from said buffer of each said active data lane to said lane merger for merging onto said parallel bus in a pre-defined repeating sequence of active data lanes.

A system for handling data comprising:

• a transmitter comprising:
• a lane distributor input from a first parallel bus;
• a plurality of transmitter buffers input by said lane distributor;
• for each transmitter buffer, an associated transmitter data lane controller input by said each transmitter buffer, each transmitter data lane controller for outputting to one data lane of a plurality of serial data lanes;
• a transmitter clock for timing any data words in any said transmitter buffer through said transmitter buffer;
• a transmit controller operatively connected to said lane distributor for establishing at least one data lane of said plurality of data lanes as an active data lane and for controlling said lane distributor to pass data words from said first parallel bus to said transmitter buffer associated with each active data lane in a pre-defined repeating sequence of active data lanes;
• a receiver, comprising:
• a receiver data lane controller for terminating each of said plurality of serial data lanes;
• a receiver buffer associated with each said receiver data lane controller;
• a lane merger associated with an output of each said receiver buffer for inputting a second parallel data bus;
• a receiver clock for timing any data words in any said receiver buffer through said receiver buffer;
• a receive controller operatively connected to each said receiver data lane controller, each said receiver buffer, and said lane merger for establishing said at least one data lane as said active data lane and for passing data words from said receiver buffer of each said active data lane to said lane merger for merging onto said second parallel bus in said pre-defined repeating sequence of active data lanes.