Memory controller and method for writing a data packet to or reading a data packet from a memory
AssigneeMediatek Inc.
InventorHsiang-I HUANG
Life of this patent
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Abstract
A memory controller and a method for data access are provided. The memory controller writes a data packet to or reads a data packet from a memory. The memory controller comprises a first register, a second register, a data packet adjuster, and a burst length determination unit. The first register stores a data bus width. The second register stores an operating frequency of the memory controller. The burst length determination unit determines a burst length according to the operating frequency. The data packet adjuster adjusts the data packet according to the data bus width and the burst length.
Claims25
A memory controller for writing a data packet to or reading a data packet from a memory, comprising:
- a first register for storing a data bus width;
- a second register for storing an operating frequency of the memory controller;
- a burst length determination unit for determining a burst length according to the operating frequency;
- and
- a data packet adjuster for adjusting the data packet according to the data bus width and the burst length;
- wherein the memory controller writes or reads the adjusted data packet in response to the burst length.
A method for writing a data packet to or reading a data packet from a memory, comprising the following steps of:
- setting a data bus width;
- determining an operating frequency of a memory controller;
- determining a burst length according to the operating frequency;
- and
- adjusting the data packet according to the data bus width and the burst length;
- wherein the adjusted data packet is written or read in response to the burst length.
Dependencies are inferred from the claim text.