Method And Apparatus For Integrated Circuit Design Model Performance Evaluation Using Basic Block Vector Clustering And Fly-By Vector Clustering

An integrated circuit (IC) design model simulator test system comprising:

• a processor;
• a memory store, coupled to the processor, the memory store including an IC design model and an original workload program exhibiting a first executable instruction length, the memory store being configured to:
• apportion the original workload program into a plurality of instruction intervals;
• generate a respective basic block vector (BBV) per instruction interval, the resultant BBVs including basic block execution count information;
• generate a respective fly-by vector (FBV) per instruction interval independent of the BBV for that same instruction interval, the resultant FBVs including microarchitecture dependent information;
• cluster the resultant BBVs into a plurality of BBV clusters, each BBV cluster representing a program phase of the original workload program;
• cluster the resultant FBVs into a plurality of FBV clusters, each FBV cluster representing a program phase of the original workload program, the clustering of FBVs being independent of the clustering of the BBVs;
• and
• generate a reduced workload program representative of the original workload program, by using information related to the BBV clusters and FBV clusters, the reduced workload program exhibiting a second executable instruction length less than the first executable instruction length.

A computer program product stored on a computer operable medium, comprising:

• instructions that apportion an original workload program into a plurality of instruction intervals, the original workload program exhibiting a first executable instruction length, the original workload program being adapted for use in a simulator test system that includes an IC design model;
• instructions that generate a respective basic block vector (BBV) per instruction interval, the resultant BBVs including basic block execution count information;
• instructions that generate a respective fly-by vector (FBV) per instruction interval independent of the BBV for that same instruction interval, the resultant FBVs including microarchitecture dependent information;
• instructions that cluster the resultant BBVs into a plurality of BBV clusters, each BBV cluster representing a program phase of the original workload program;
• instructions that cluster the resultant FBVs into a plurality of FBV clusters, each FBV cluster representing a program phase of the original workload program, the clustering of FBVs being independent of the clustering of the BBVs;
• and
• instructions that generate a reduced workload program representative of the original workload program, by using information related to the BBV clusters and FBV clusters, the reduced workload program exhibiting a second executable instruction length less than the first executable instruction length.