Method and Apparatus For Evaluating Integrated Circuit Design Performance Using Basic Block Vectors, Cycles Per Instruction (CPI) Information and Microarchitecture Dependent Information

An integrated circuit (IC) design model simulator test system comprising:

• a processor;
• a memory store, coupled to the processor, the memory store including an IC design model and a first workload program including instructions, the memory store being configured to:
• execute the first workload program on the IC design model;
• generate basic block vectors (BBVs) while executing the first workload program, each BBV corresponding to a respective BBV instruction interval of the first workload program;
• cluster the BBVs by program phase of the first workload program;
• store microarchitecture dependent error information that indicates microarchitecture dependent errors of different types that the simulator test system produces during the BBV instruction intervals of the first workload program;
• and
• generate a weighted error rate including a cycles per instruction (CPI) error rate and weighted microarchitecture dependent error rate information.

A computer program product stored on a computer operable medium, comprising:

• instructions that execute the first workload program on the IC design model;
• instructions that generate basic block vectors (BBVs) while executing the first workload program, each BBV corresponding to a respective BBV instruction interval of the first workload program;
• instructions that cluster the BBVs by program phase of the first workload program;
• instructions that store microarchitecture dependent error information that indicates microarchitecture dependent errors of different types that the simulator test system produces during the BBV instruction intervals of the first workload program;
• and
• instructions that generate a weighted error rate including a cycles per instruction (CPI) error rate and weighted microarchitecture dependent error rate information.