Method, device, and system for pre-memory symmetric multiprocessing flow
AssigneeIntel Corporation
InventorsVincent J. ZIMMER, Palsamy Sakthikumar
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Abstract
A cache-as-RAM (CAR) system of a multi-processor system that includes a plurality of processors may be initialized. The CAR system may assign a physical data address range for each of the plurality of processors such that the physical data address ranges allocated to all of the plurality of processors overlap with each other. A boot code stream may be executed with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream. Other embodiments are described and claimed.
Claims22
A method comprising:
- initializing a cache-as-RAM (CAR) system in a multi-processor system, the multi-processor system including at least a plurality of processors, each processor associated with a memory;
- the CAR system assigning a physical data address range for each of the plurality of processors, such that the physical data address ranges allocated to all of the plurality of processors overlap with each other;
- and
- executing a boot code stream with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream.
A device comprising:
- a plurality of processors each associated with a portion of memory, one or more of the plurality of processors to initialize a cache-as-RAM (CAR) system, to assign by the CAR system a tile for each of a plurality of processors such that the tiles allocated to all of the plurality of processors overlap with each other, and to execute a boot code stream with the CAR appearing to the executing boot stream as a memory store for executing the boot code stream.
A system comprising:
- a plurality of processors each associated with a memory, one or more of the plurality of processors to initialize a cache-as-RAM (CAR) system, to assign by the CAR system a physical data address range for each of the plurality of processors such that the physical data address ranges allocated to all of the plurality of processors overlap with each other, and to execute a boot code stream with the CAR accessed by the executing boot stream as a memory store for executing the boot code stream;
- and
- an interconnect network to connect the plurality of processors.
A processor-readable storage medium having stored thereon instructions that, if executed by a processor, cause the processor to perform a method comprising:
- initializing a cache-as-RAM (CAR) system in a multi-processor system, the multi-processor system including at least a plurality of processors, each processor associated with a memory;
- the CAR system assigning a tile for each of the plurality of processors, such that the tiles allocated to all of the plurality of processors overlap with each other;
- and
- a boot code stream accessing the CAR as a memory store for execution.
Dependencies are inferred from the claim text.