Limiter Based Analog Demodulator
AssigneeMarvell World Trade Ltd.
InventorsZhongxuan Zhang, Lixin Zhao, Steve Xuefeng Jiang
Life of this patent
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Abstract
A phase detector includes a decimator to decimate a digitized in-phase signal and a digitized quadrature signal to N times a symbol rate, where N is an integer greater than one. A burst detector to detect bursts in an output of the decimator. A carrier offset block to determine an offset angle based on an output of the burst detector. A rotator to generate a rotated signal by rotating the output of the decimator based on the offset angle determined by the carrier offset block. An equalizer to perform coherent demodulation of the rotated signal.
Claims13
A phase detector, comprising:
- a decimator to decimate a digitized in-phase signal and a digitized quadrature signal to N times a symbol rate, where N is an integer greater than one;
- a burst detector to detect bursts in an output of the decimator;
- a carrier offset block to determine an offset angle based on an output of the burst detector;
- a rotator to generate a rotated signal by rotating the output of the decimator based on the offset angle determined by the carrier offset block;
- and
- an equalizer to perform coherent demodulation of the rotated signal.
A phase detector, comprising:
- a decimator to decimate a digitized in-phase signal and a digitized quadrature signal to N times a symbol rate, where N is an integer greater than one;
- a burst sync block to detect bursts in an output of the decimator;
- a time division multiple access (TDMA) block to generate a slot timing signal based on an output of the burst sync block;
- and
- a clock recovery block to estimate a timing offset based on the slot timing signal;
- an interpolator to perform timing adjustment and rate conversion based on the timing offset;
- an arctangent block to convert an output of the interpolator into a phase signal;
- a carrier recovery block to perform carrier offset adjustment of the phase signal to generate an adjusted phase signal;
- and
- a decoder block to decode the adjusted phase signal.
A phase detector including:
- a decimator to decimate a digitized in-phase signal and a quadrature signal to N times the symbol rate, where N is an integer greater than one;
- a burst sync block to detect a burst based on an output of the decimator;
- a time division multiple access (TDMA) block to generate a slot timing signal based on an output of the burst sync block;
- a clock recovery block to estimate a timing offset based on the slot timing signal;
- an interpolator to perform timing adjustment and rate conversion based on the timing offset;
- an arctangent block to convert an output of the interpolator into a phase signal;
- a carrier recovery block to perform carrier offset adjustment of the phase signal to generate an adjusted phase signal;
- and
- a decoder block to decode the adjusted phase signal.
Dependencies are inferred from the claim text.