Semiconductor memory device and test method thereof

A test method of a semiconductor memory device comprising a memory cell array having a plurality of memory cells arranged at intersections of a plurality of word lines and a plurality of bit lines, a first sense amplifier connected to a bit line at a predetermined position of the plurality of bit lines, a second sense amplifier connected to a bit line adjacent to the bit line at the predetermined position, and a supplying circuit for supplying a predetermined voltage to each bit line connected to the first or second sense amplifier, the method comprising:

• stopping an operation of either of the first and second sense amplifiers;
• supplying a predetermined voltage to a bit line connected to the stopped sense amplifier;
• activating a selected word line;
• operating the other of the first and second sense amplifiers so as to amplifier a voltage difference transmitted to a bit line connected thereto;
• and
• performing a test by detecting outputted read data.

A semiconductor memory device comprising:

• a first bit line and a second bit line adjacent to the first bit line;
• a first memory cell connected to the first bit line and a second memory cell connected to the second bit line;
• a first sense amplifier connected to the first bit line and a second sense amplifier connected to the second bit line;
• and
• a control circuit that activates the second sense amplifier while deactivating the first sense amplifier when each of the first and second memory cells is selected.