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US 2009/0268533 A1Published application
Sensing delay circuit and semiconductor memrory device using the same
AssigneeHynix Semiconductor Inc.
InventorSang Il Park
Life of this patent
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Abstract
A sensing delay circuit includes a logic element which responds to a test mode signal to transfer a start signal, a delay unit which is configured of a plurality of inverters having MOS transistors with controlled threshold voltage, and receives external voltage as bulk voltage and delays an output signal from the logic element by a predetermined period, and a buffer which responds to an output signal from the delay unit to buffer the output signal from the logic element and output it.
Claims25
A sensing delay circuit includes:
- a logic element configured to respond to a test mode signal to transfer a start signal;
- a delay unit including a plurality of inverters having MOS transistors with controlled threshold voltage and configured to receive external voltage as bulk voltage and delay an output signal from the logic element by a predetermined period;
- and
- a buffer configured to respond to an output signal from the delay unit to buffer the output signal from the logic element and output the buffered signal.
1 more element
A sensing delay circuit comprising:
- a first sensing delay unit including MOS transistors with controlled threshold voltage, and configured to receive internal voltage as bulk voltage, control an enable period of a start signal in response to a test mode signal, and generate a sense amplifier enable signal;
- and
- a second sensing delay unit including MOS transistors with controlled threshold voltage, and configured to receive external voltage as the bulk voltage, control the enable period of the start signal in response to the test mode signal, and generate the sense amplifier enable signal.
A semiconductor memory device including:
- a sensing delay circuit including a MOS transistor with controlled threshold voltage, and configured to receive either internal voltage or external voltage as bulk voltage, control an enable period of a start signal in response to a test mode signal, and generate a sense amplifier enable signal;
- and
- a sense amplifier configured to receive, and be driven by, the sense amplifier enable signal.
Dependencies are inferred from the claim text.