Novel SRAM Cell Array Structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsCheng-Hung Hung Lee, Ching-Wei Wu, Hung-Jen Liao
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Abstract
This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
Claims20
A static random access memory (SRAM) cell array structure comprising:
- a first and second conductive line coupled to a column of SRAM cells, the first and second conductive lines being substantially parallel to each other and formed by a first metal layer;
- and
- a third conductive line placed between the first and second conductive lines, and spanning across the column of SRAM cells without making conductive coupling thereto, the third conductive line being also formed by the first metal layer.
The SRAM cell array structure of claim 9, wherein during a write operation, voltage at the fourth conductive line stays at a high voltage (Vcc) while the third conductive line swings from the Vcc to a low voltage (Vss).
A static random access memory (SRAM) cell array structure comprising:
- a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, wherein during a write operation, voltage at one of the bit-lines swings from a high voltage (Vcc) to a low voltage (Vss), while voltage at the other bit-line stays at the Vcc;
- and
- a first conductive line placed between the first and second bit-lines, and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
A static random access memory (SRAM) cell array structure, the SRAM cell
- having six or more transistors, the SRAM cell array structure comprising:
- a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, wherein during a write operation, voltage at one of the bit-lines swings from a high voltage (Vcc) to a low voltage (Vss), while voltage at the other bit-line stays at the Vcc;
- and
- a first conductive line placed between the first and second bit-lines, and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer.
Dependencies are inferred from the claim text.