Receiver capable of generating audio reference clock

A reception-side electronic device for use in a system with a transmission-side electronic device transmitting a sampling frequency, a first natural number, and a second natural number to a reception-side electronic device, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the reception-side electronic device comprising:

• a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, wherein,
• the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.

A system for transmitting/receiving video and audio data, comprising:

• a transmitter for transmitting a sampling frequency, a first natural number, and a second natural number, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock;
• and
• a receiver for receiving the pixel clock, the sampling frequency, the first natural number, and the second natural number transmitted by the transmitter, wherein,
• the receiver includes:
• a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, and
• the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.

A semiconductor circuit includible in a receiver for use in a system with a transmitter transmitting a sampling frequency, a first natural number, and a second natural number to a receiver, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the circuit comprising:

• a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, wherein,
• the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.

A macro for use in a semiconductor circuit includible in a receiver for use in a system with a transmitter transmitting a sampling frequency, a first natural number, and a second natural number to a receiver, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the macro comprising:

• a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, wherein,
• the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.

A method for generating a desired audio reference clock for use on a receiver side in a system with a transmitter transmitting a sampling frequency, a first natural number, and a second natural number to a receiver, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the method comprising:

• outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder;
• and
• calculating a sum of remainders as necessary when outputting the second signal, and controlling the cycles of the second signal when the sum exceeds a threshold.

A frequency divider having provided thereto a pixel clock, a first natural number, and a second natural number, the divider comprising:

• a first frequency divider for outputting a first signal by dividing a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• a cycle control portion for outputting a second signal having first and second cycles included within a cycle of the first signal by controlling a cycle of the pixel clock, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the first signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the first signal corresponding to the remainder, wherein,
• the cycle control portion calculates a sum of remainders as necessary, and controls the cycles of the second signal when the sum exceeds a threshold.

A storage medium having stored therein a program executable on a computer device for use in a system with a transmitter transmitting a sampling frequency, a first natural number, and a second natural number to a receiver, along with a pixel clock required for video data reproduction, the first natural number and the second natural number being a numerator and a denominator, respectively, in a rational relationship where a frequency of the pixel clock is divided by a frequency of an audio reference clock, the program causing the computer device to:

• divide a signal with a frequency corresponding to the pixel clock or an integral multiple thereof by a reciprocal of an integral multiple of the first natural number, the integral multiple of the first natural number being greater than or equal to 1;
• and
• control a cycle of the pixel clock such that first and second cycles are included within a cycle of the divided signal, the first cycle corresponding to a quotient which, along with a remainder, results from the integral multiple of the first natural number divided by a third natural number equal to or different from the second natural number, the number of first cycles included within the cycle of the divided signal corresponding to a first value for the third natural number minus the remainder, the second cycle corresponding to a second value for the quotient plus 1, the number of second cycles included within the cycle of the divided signal corresponding to the remainder, wherein,
• the computer device is caused to calculate a sum of remainders as necessary in preparation for controlling the cycle of the pixel clock, such that the cycle of the pixel clock is controlled when the sum exceeds a threshold.