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US 2009/0267671 A1Published application
Optimization of library slew ratio based circuit
AssigneeLSI Corporation
InventorJeffrey Scott Brown
Life of this patent
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Abstract
Disclosed is a technique for providing minimal sequential overhead in a flip-flop circuit. Equalization of setup times is achieved in one embodiment. In addition, delays in clock to Q can be equalized for both rising data transitions and falling data transitions. Large setup times are not required since optimization techniques equalize setup times for both rising and falling data transitions.
Claims6
A method of minimizing sequential overhead in a latching circuit design comprising:
- generating a library representation of slew rates for rising and falling data transitions;
- creating an initial latching circuit design;
- performing parasitic extraction of said initial latching circuit design;
- optimizing device widths of components of said initial latching current design by less than approximately 15 percent of device widths of said initial latching circuit design to generate a timing optimized latching circuit that is substantially input transition direction independent;
- generating a layout of said optimized latching circuit;
- recharacterizing said altered layout of said optimized latching circuit.
3 more elements
A latching circuit that has reduced sequential overhead comprising:
- a first pass-gate that has an N-channel device that has a device width that has been substantially optimized using hspice optimization routines, and a P-channel device that has a device width that has been substantially optimized from an initial circuit layout using hspice optimization routines;
- a master loop having an inverter that has a P-channel device that has a device width that has been substantially optimized, and an N-channel device that has a device width that has been substantially optimized, from an initial circuit layout using hspice optimization routines;
- a second pass-gate that has an N-channel device that has a device width that has been substantially optimized from an initial circuit layout and a P-channel device that has been substantially optimized from an initial circuit layout, using hspice optimization routines;
- a slave loop having a second inverter that has a P-channel device that has been substantially optimized from an initial circuit layout and an N-channel device that has been substantially optimized from an initial circuit layout, using hspice optimization routines.
1 more element
Dependencies are inferred from the claim text.