Semiconductor memory device for generating a delay locked clock in early stage

A semiconductor memory apparatus, comprising:

• a first delay line configured to delay a system clock;
• a first delay model configured to delay an output of the first delay line by a modeled delay time to generate a first feedback clock;
• a first phase comparator configured to compare a phase of the first feedback clock with that of the system clock;
• a first shift register configured to control a delay amount of the first delay line according to a comparison result of the first phase comparator;
• a second delay line configured to delay the system clock;
• a second delay model configured to delay an output of the second delay line by the modeled delay time to generate a second feedback clock;
• a second phase comparator configured to compare a phase of the second feedback clock with that of the system clock;
• a second shift register configured to control a delay amount of the second delay line according to a comparison result of the second phase comparator;
• a first locked detector configured to output a first locking signal to the clock selection block when the phase of the first feedback clock is the same as that of the system clock;
• a second locked detector configured to output a second locking signal to the clock selection block when the phase of the second feedback clock is the same as that of the system clock;
• and
• a clock selection block configured to select one of the first and second delay locked clocks in response to the first and second locking clocks to thereby output a reference clock for data output.

A semiconductor memory apparatus, comprising:

• a first delay line configured to delay a system clock;
• a second delay line configured to delay the system clock;
• a delay model configured to delay outputs of the first and second delay lines by a modeled delay time respectively to generate first and second feedback clocks;
• a phase comparator configured to compare phases of the first and second feedback clocks with that of the system clock respectively;
• a delay line controller configured to control delay amounts of the first and second delay lines according to comparison results of the phase comparator;
• and
• a clock selection circuit configured to select one of the first and second delay locked clocks based on the comparison results to thereby output a reference clock for data output.

A method for generating a reference clock for data access, comprising:

• delaying outputs of the first and second delay lines by a modeled delay time respectively to generate first and second feedback clocks;
• comparing phases of the first and second feedback clocks with that of a system clock respectively;
• determining delay amounts of the first and second delay lines according to comparison results of the phase comparator;
• in the first and second delay lines, respectively delaying input clocks by the delay amounts;
• and
• selecting one of the first and second delay locked clocks based on the comparison results to thereby output a reference clock for data output.