Pll circuit
AssigneesRenesas Electronics Corporation, Epoch Microelectronics, Inc.
InventorsToshiya UOZUMI, Keisuke Ueda, Mitsunori Samata, Satoru Yamamoto, Russell P. Mohn, Aleksander Dec, Ken Suyama
Life of this patent
Estimating the term…
Loading patent…
AssigneesRenesas Electronics Corporation, Epoch Microelectronics, Inc.
InventorsToshiya UOZUMI, Keisuke Ueda, Mitsunori Samata, Satoru Yamamoto, Russell P. Mohn, Aleksander Dec, Ken Suyama
Estimating the term…
In an ADPLL composed of a digital circuit, a technique improving phase difference detection in a vicinity of a phase difference of 0 (zero) is provided. A feedback loop comprises a PFD comparing phases and frequencies of a reference signal and a feedback signal, a TDC converting an output of the PFD into a digital value, a DLF removing a high frequency noise component from an output of the TDC, a DCO controlled based on an output of the DLF and a DIV frequency-dividing an output the DCO and outputting the feedback signal. An offset value is added at any portion of the feedback loop, a phase of the feedback signal is controlled and a value other than 0 is inputted to the TDC even when the ADPLL is locked.
A PLL circuit configured by a feedback loop comprising:
A PLL circuit configured by a feedback loop including:
A PLL circuit configured by a feedback loop comprising:
Dependencies are inferred from the claim text.