Electronic system that adjusts dll lock state acquisition time
AssigneeQimonda North America Corp.
InventorJason Varricchione
Life of this patent
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Abstract
One embodiment provides an electronic system including a delay locked loop and a control circuit. The delay locked loop is configured to be enabled and update lock state data and to be disabled and store the locked state data. The control circuit is configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period. The control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.
Claims28
An electronic system comprising:
- a delay locked loop configured to be enabled and update lock state data and to be disabled and store the lock state data;
- and
- a control circuit configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period, wherein the control circuit controls the length of the update interval and the length of the enable period to adjust lock state acquisition time for the delay locked loop in exiting the standby mode.
An electronic system comprising:
- a delay locked loop configured to be enabled and update lock state data and to be disabled and store the lock state data;
- and
- a control circuit configured to periodically enable the delay locked loop in standby mode at an update interval and for an enable period, wherein the control circuit enables the delay locked loop for the enable period to obtain partial lock state data corresponding to a partial lock state of the delay locked loop and updates the lock state data to the partial lock state data.
An integrated circuit comprising:
- a delay locked loop including a fine delay line and a coarse delay line;
- and
- a control circuit configured to switch the fine delay line into the delay locked loop in normal mode and to switch the fine delay line out of the delay locked loop and the coarse delay line into the delay locked loop in standby mode.
An integrated circuit comprising:
- means for aligning a first clock signal and a second clock signal via lock state data;
- means for updating the lock state data;
- means for storing the lock state data;
- means for periodically updating the lock state data in standby mode at an update interval and for an enable period;
- and
- means for controlling the length of the update interval and the length of the enable period to adjust power consumption during the standby mode and to adjust lock state acquisition time in exiting the standby mode.
A method of operating a delay locked loop, comprising:
- aligning a first clock signal and a second clock signal via lock state data;
- storing the lock state data;
- periodically updating the lock state data in standby mode during an enable period and at an update interval;
- and
- adjusting the length of the update interval and the length of the enable period to adjust lock state acquisition time in exiting the standby mode.
A method of operating a delay locked loop, comprising:
- enabling the delay locked loop to update lock state data;
- disabling the delay locked loop in entering standby mode;
- storing the lock state data in entering the standby mode;
- periodically enabling the delay locked loop in the standby mode at an update interval and for an enable period to obtain partial lock state data corresponding to a partial lock state of the delay locked loop;
- and
- updating the lock state data to the partial lock state data.
A method of operating a delay locked loop, comprising:
- switching a fine delay line into the delay locked loop in normal mode;
- switching the fine delay line out of the delay locked loop in standby mode;
- and
- switching a coarse delay line into the delay locked loop in the standby mode.
Dependencies are inferred from the claim text.