Clock Gating System and Method

An apparatus comprising:

• a semiconductor device comprising:
• an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;
• a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal;
• and
• a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

An apparatus comprising:

• input logic means for receiving at least one input signal and providing an output coupled to an internal enable node;
• keeper means for selectively holding a logical voltage level at the internal enable node, the keeper means including at least one switching element that is responsive to a gated clock signal;
• and
• gating means for generating the gated clock signal, wherein the gating means is responsive to an input clock signal and to the logical voltage level at the internal enable node.

A method comprising:

• receiving at least one input signal at an input logic circuit having at least one input and having an output coupled to an internal enable node;
• generating a gated clock signal at a gating element that is responsive to an input clock signal and to a logical voltage level at the internal enable node;
• and
• selectively holding the logical voltage level at the internal enable node in response to the gated clock signal.

A method comprising:

• a first step for receiving at least one input signal at an input logic circuit having at least one input and an output coupled to an internal enable node;
• a second step for generating a gated clock signal at a gating element that is responsive to an input clock signal and to a logical voltage level at the internal enable node;
• and
• a third step for selectively holding the logical voltage level at the internal enable node in response to the gated clock signal.

A method comprising:

• receiving design information representing at least one physical property of a semiconductor device, the semiconductor device including:
• an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;
• a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal;
• and
• a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal;
• transforming the design information to comply with a file format;
• and
• generating a data file including the transformed design information.

A method comprising:

• receiving design information including physical positioning information of a packaged semiconductor device on a circuit board, the packaged semiconductor device including a semiconductor structure comprising:
• an input logic circuit having at least one input to receive at least one input signal and having an output coupled to an internal enable node;
• a keeper circuit coupled to selectively hold a logical voltage level at the internal enable node, the keeper circuit including at least one switching element that is responsive to a gated clock signal;
• and
• a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal;
• and
• transforming the design information to generate a data file.