Apparatus, System and Method of Power State Control

A method of asynchronously increasing power to a power domain, comprising:

• receiving an awaken command for a selected power domain;
• providing a power domain on signal to said power domain upon receiving said awaken command;
• determining whether a power domain good status signal has been received;
• providing a non-retention command and a non-isolation command after receiving said negative power good status signal;
• and
• receiving, upon receiving said awaken command, an affirmative isolation status signal denoting that an isolation of said power domain has occurred.

An apparatus for asynchronously selecting a power level in a memory chip area, comprising:

• a first combinational logic and a second combinational logic;
• a sleep input coupled to said first and second combinational logic;
• a retention status input and an isolation status input coupled to said first and second combinational logic;
• and
• a power status input denoting whether all power that is applied to said power domain is on, said first combinational logic providing a power domain signal to said power domain when combining at least said sleep input, said retention status input and said isolation status input, and said second combinational logic providing a retention and isolation command when combining at least said sleep input, said retention status input and said isolation status input.

A system for asynchronously controlling power to be applied to a power domain, comprising:

• a power switch coupled to at least two different power levels;
• a retention cell coupled to said power switch;
• an isolation cell coupled to said retention cell;
• and
• an asynchronous power controller that receives:
• an isolation status signal, received from said isolation cell, that denotes whether an isolation of said memory area has occurred,
• a retention status signal, received from said retention cell, that denotes whether a retention area in said power domain has stored data, and
• a power status signal that denotes whether all power applied to said memory area is in a same state, said power controller providing a power domain command to said power switch when sequentially combining an isolation status signal, a retention status signal and a power status signal.

A method of employing a power state controller:

• receiving a plurality of power domain commands;
• providing a combined enable command from a combination of said plurality of enable power domain commands;
• latching said combined enable command on a first edge of a clock signal;
• providing said combined enable command to at least one power switch on a reference clock status;
• and
• transitioning said clock cycle to a second edge of the same clock cycle.