US 2009/0267229 A1 · CHIP PACKAGE STRUCTURE

Abstract

A chip package structure is provided. The chip package structure comprises different layers of leads electrically connected to different circuits of a chip. The chip package structure comprises a chip and a flexible substrate layer. The chip has an active surface, a plurality of first pads, and a plurality of second pads. The first pads and the second pads are disposed on the active surface. The flexible substrate layer has a first conductive layer, a second conductive layer, a first surface, and a second surface opposite the first surface. The flexible substrate layer has an opening defined therein. The first conductive layer is formed on the first surface of the flexible substrate layer. The first conductive layer includes a plurality of first leads. The first leads electrically connect to the first pads. The second conductive layer is formed on the second surface of the flexible substrate layer. The second conductive layer includes a plurality of second leads. The second leads extend inwards into the opening and electrically connect to the second pads through the opening.

Claims20

Dependent claims

A chip package structure, comprising:

a chip, having an active surface, a plurality of first pads, and a plurality of second pads, the first pads and the second pads being disposed on the active surface;
a flexible substrate layer, having a first surface, and a second surface opposite the first surface, and the flexible substrate layer defining an opening therein;
a first conductive layer, being formed on the first surface of the flexible substrate layer, the first conductive layer having a plurality of first leads, the first leads being electrically connected to the first pads;
and
a second conductive layer, being formed on the second surface of the flexible substrate layer, the second conductive layer having a plurality of second leads, the second leads extending inward into the opening and being electrically connected to the second pads through the opening.

2 more elements

A chip package structure, comprising:

a chip, having an active surface, a plurality of first pads, and a plurality of second pads, wherein the first pads and the second pads are disposed on the active surface;
a first flexible substrate layer, having a first surface and a second surface opposite the first surface, and the first flexible substrate layer defining a first opening therein;
a first conductive layer, being formed on the first surface of the first flexible substrate layer, the first conductive layer having a plurality of first leads, the first leads being adapted to be electrically connected to the first pads;
a second flexible substrate layer, having a first surface and a second surface opposite the first surface, the first surface of the second flexible substrate layer being facing the second surface of the first flexible substrate layer, the second flexible substrate layer being formed on the first flexible substrate layer, the second flexible substrate layer defining a chip bonding area on the first surface thereof, the chip bonding area being located in the first opening;
and
a second conductive layer, being formed on the first surface of the second flexible substrate layer, the second conductive layer having a plurality of second leads, the second leads extending inward into the first opening and being electrically connected to the second pads through the first opening.

3 more elements

Dependencies are inferred from the claim text.

Chip package structure

Life of this patent

Chip package structure

Life of this patent

Abstract

Claims20