Mosfet device having dual interlevel dielectric thickness and method of making same

A metal-oxide-semiconductor (MOS) device, comprising:

• a semiconductor layer of a first conductivity type, the semiconductor layer having source and drain regions of a second conductivity type, a channel region and a lightly dope drain region formed therein;
• a gate formed proximate an upper surface of the semiconductor layer over the channel region;
• a dielectric layer formed along the upper surface of the semiconductor layer, wherein the dielectric layer has a region of reduced thickness covering a portion of the gate and extending to cover a portion of the lightly-doped drain region proximate the gate;
• and
• a shielding electrode formed conformably over the dielectric layer and extending from over an upper surface of the gate to a point laterally beyond the region of reduced thickness.

A method of forming a laterally diffused metal-oxide-semiconductor (LDMOS) device, comprising:

• forming a semiconductor layer of a first conductivity type having source and drain regions of a second conductivity type, a channel region and a lightly-doped drain region formed therein;
• forming a gate and a gate dielectric layer over the channel region proximate an upper surface of the semiconductor layer;
• after the forming steps, depositing a first interlevel dielectric layer over an upper surface of the semiconductor layer, the first interlevel dielectric layer formed to a thickness effective for reducing gate-to-drain parasitic capacitance in the LDMOS device;
• etching the first dielectric layer to form an opening in the first dielectric layer overlapping at least a part of an upper surface of the gate and a part of the lightly-doped drain proximate to the gate;
• conformably depositing a second dielectric layer having a second thickness over the first dielectric layer, the second thickness being less than the first thickness;
• and
• conformably depositing a conductive layer over the second dielectric layer and etching the conductive layer to form a shielding electrode, the shielding electrode extending at least partially over the gate to a point over the lightly-doped drain region past the opening, wherein the second thickness is selected to space the shielding electrode from the upper surface of the semiconductor layer a distance effective for reducing hot carrier injection in the gate dielectric layer.