Semiconductor device and method for manufacturing the same

A method for manufacturing a charge trap type non-volatile memory device having memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend, comprising:

• stacking at least a tunnel insulating film material, a charge film material, and a buffer film material on the silicon substrate;
• forming the element isolation trenches that extend from the buffer film material to the silicon substrate by etching the buffer film material, the charge film material, the tunnel insulating film material, and the silicon substrate;
• forming each of the memory cells as a memory cell having a tunnel insulating film, a charge film, and a buffer film that covers the charge film;
• depositing an element isolation insulating film in each of the element isolation trenches;
• etching each of the element isolation insulating films so that an upper surface of each of the element isolation insulating films comes near to an interface between each of the buffer films and each of the charge films;
• removing each of the buffer films;
• and
• etching each of the element isolation insulating films so that an upper portion of a side wall of each of the element isolation insulating films contacts with a side wall of the charge film in each of the memory cells.

A method for manufacturing a charge trap type non-volatile memory device having memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend, comprising:

• stacking at least a tunnel insulating film material, a charge film material, an etching protective film material, and a buffer film material on the silicon substrate;
• forming the element isolation trenches that extend from the buffer film material to the silicon substrate by etching the buffer film material, the etching protective film material, the charge film material, the tunnel insulating film material, and the silicon substrate;
• forming each of the memory cells as a memory cell having a tunnel insulating film, a charge film, and an etching protective film and a buffer film that cover the charge film;
• depositing each of the element isolation insulating films in each of the element isolation trenches;
• etching each of the element isolation insulating films so that an upper surface of each of the element isolation insulating films comes near to an interface between each of the buffer films and each of the etching protective films;
• removing each of the buffer films and each of the etching protective films;
• and
• etching each of the element isolation insulating films so that an upper portion of a side wall of each of the element isolation insulating films contacts with a side wall of each of the charge films.

A method for manufacturing a charge trap type non-volatile memory device having:

• a memory cell array section comprising memory cells formed on a silicon substrate at a predetermined interval via an element isolation trench along a first direction in which word lines extend;
• and
• a select gate section comprising select gate transistors formed on the silicon substrate at a predetermined interval via a select gate transistor isolation trench along the first direction, comprising:
• stacking at least a tunnel insulating film material, a charge film material, an etching protective film material, and a buffer film material on the silicon substrate in both of the memory cell array section and the select gate section;
• etching the buffer film material, the etching protective film material, the charge film material, the tunnel insulating film material, and the silicon substrate in both of the memory cell array section and the select gate section so that:
• forming the element isolation trenches of the memory cell array section extend from the buffer film material to the silicon substrate, and forming each of the memory cells having a tunnel insulating film, a charge film, and an etching protective film and a buffer film that cover the charge film;
• and
• forming the select gate transistor isolation trenches of the select gate section extend from the buffer film material to the silicon substrate, and forming each of the select gate transistors having a tunnel insulating film, a charge film, and an etching protective film and a buffer film that cover the charge film;
• depositing an insulating film material in the element isolation trenches of the memory cell array section and in the select gate transistor isolation trenches of the select gate section, and thereby forming the element isolation insulating films of the memory cell array section and the select gate transistor isolation insulating films of the select gate section;
• etching each of the element isolation insulating films and each of the select gate transistor isolation insulating films so that an upper surface of each of the element isolation insulating films in the memory cell array section and an upper surface of each of the select gate transistor isolation insulating films in the select gate section come near to an interface between the buffer film and the etching protective film;
• removing the buffer films in both of the memory cell array section and the select gate section;
• removing the charge films and the etching protective films in the select gate section;
• removing the etching protective films in the memory cell array section and etching each of the element isolation insulating films so that an upper portion of a side wall of each of the element isolation insulating films in the memory cell array section contacts with a side wall of each of the charge films;
• and
• removing the tunnel insulating films in the select gate section.