Structure and process integration for flash storage element and dual conductor complementary mosfets

A method of simultaneously fabricating a flash storage element, an n-type field effect transistor (FET) and a p-type FET of a semiconductor element, comprising:

• (a) depositing a first gate dielectric and a first gate metal layer overlying the first gate dielectric and patterning the first gate metal layer with the first gate dielectric to overlie first and second active semiconductor areas of a substrate but not overlie a third active semiconductor area of the substrate;
• (b) depositing a second gate dielectric and a second gate metal layer overlying the second gate dielectric and patterning the second gate metal layer with the second gate dielectric to overlie the first and third active semiconductor areas but not overlie the second active semiconductor area;
• (c) simultaneously forming first, second and third gates overlying the first, second and third active semiconductor areas, respectively, by processing including depositing and patterning a semiconductor layer;
• and
• (d) forming source and drain regions of the flash storage element, the n-type FET and the p-type FET in the first, second and third active semiconductor areas, respectively.