Integrated circuit having efficiently packed decoupling capacitors

A method of standard cell design of an integrated circuit comprising a substrate having a semiconducting surface, a plurality of standard cells arranged in a plurality of rows comprising at least a first row and a second row immediately above said first row, said first row comprising at least a first of said standard cells, said first standard cell comprising a first decap filler cell comprising at least a first MOS transistors having a gate electrode on a thick gate dielectric on said surface connected as a decoupling capacitor, said second row comprising at least a second of said standard cells, said second standard cell comprising a second decap filler cell comprising at least a second MOS transistors having a gate electrode on said thick gate dielectric on said surface connected as a decoupling capacitor, comprising:

• placing a plurality of circuit elements including said plurality of standard cells comprising a plurality of standard cell gates in a circuit layout for said integrated circuit and placing a plurality of decap filler cells including said first and second decap filler dells in at least some locations in said integrated circuit unused by said standard cell gates using design rules including a first minimum spacing between thick gate dielectric mask regions for adjacent cells;
• expanding at least one dimension of said thick gate dielectric mask for said plurality of decap filler cells to cause a violation of said first minimum spacing between said first and second decap filler cells, and
• placing a gap fill portion to add a thick gate dielectric mask portion across a border between said first and second decap filler cells to remove said violation.

An integrated circuit formed by formed by a high efficiency decap filler circuit design process, comprising:

• an integrated circuit comprising:
• a substrate having a semiconducting surface;
• a plurality of standard cells arranged in a plurality of rows comprising at least a first row and a second row immediately above said first row;
• said first row comprising at least a first of said standard cells, said first standard cell comprising a first decap filler cell comprising a first active area and a field dielectric outside said first active area having a portion with a full field dielectric thickness portion and a portion with a thinned field dielectric, and at least a first MOS transistors having a gate electrode on a thick gate dielectric on said first active area connected as a decoupling capacitor, and
• said second row comprising at least a second of said standard cells, said second standard cell comprising a second decap filler cell comprising a second active area and a field dielectric having a portion having said full field dielectric thickness and a portion having said thinned field dielectric portion, at least a second MOS transistors having a gate electrode on said thick gate dielectric on said second active area connected as a decoupling capacitor;
• wherein said thinned field dielectric extends from said first decap filler cell to said second decap filler cell across a border between said first and second decap filler cell,
• said integrated circuit formed by a process comprising:
• printing a pattern for said thick gate dielectric using a thick gate dielectric mask having at least one feature extending from said first decap filler cell to said second decap filler cell across said border between said first and second decap filler cells.

An integrated circuit formed by formed by a high efficiency decap filler circuit design process, comprising:

• an integrated circuit comprising:
• a substrate having a semiconducting surface;
• a plurality of standard cells arranged in a plurality of rows comprising at least a first row and a second row immediately above said first row;
• said first row comprising at least a first of said standard cells, said first standard cell comprising a first decap filler cell comprising a first active area and a field dielectric outside said first active area having a portion with a full field dielectric thickness portion and a portion with a thinned field dielectric, and at least a first MOS transistors having a gate electrode on a thick gate dielectric on said first active area connected as a decoupling capacitor, and
• said second row comprising at least a second of said standard cells, said second standard cell comprising a second decap filler cell comprising a second active area and a field dielectric having a portion having said full field dielectric thickness and a portion having said thinned field dielectric portion, at least a second MOS transistors having a gate electrode on said thick gate dielectric on said second active area connected as a decoupling capacitor;
• wherein said thinned field dielectric extends from said first decap filler cell to said second decap filler cell across a border between said first and second decap filler cell, and
• wherein a total distance between said first MOS transistor in said first decap filler cell and said second MOS transistor in said second decap filler cell is at least 10% less than (i) two times a design rule minimum for overlap of said thick gate dielectric with an active area of said transistors and (ii) a design rule minimum spacing between thick gate dielectric regions in adjacent ones of said standard cells.