Signal output device, signal detection device, tester, electron device, and program

A signal detecting apparatus for detecting a pattern signal input thereto, comprising:

• a first comparing section that detects a logic value of the pattern signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the pattern signal in accordance with a second timing signal having a different phase from the first timing signal;
• a selection control section that detects a waveform pattern of the pattern signal based on one of (i) the logic value of the pattern signal detected by the first comparing section and (ii) the logic value of the pattern signal detected by the second comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the pattern signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the pattern signal, and outputs the selected logic value.

A signal detecting apparatus for detecting a pattern signal input thereto, comprising:

• a first comparing section that detects a logic value of the pattern signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the pattern signal in accordance with a second timing signal having a different phase from the first timing signal;
• a third comparing section that detects a logic value of the pattern signal at a substantially middle timing of each cycle of the pattern signal;
• a selection control section that detects a waveform pattern of the pattern signal based on the logic value of the pattern signal detected by the third comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the pattern signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the pattern signal, and outputs the selected logic value.

A test apparatus for testing a device under test, comprising:

• a signal generating apparatus that inputs a pattern signal into the device under test;
• a signal detecting apparatus that detects an output signal output from the device under test;
• and
• a judging section that judges whether the device under test is acceptable based on the output signal detected by the signal detecting apparatus, wherein
• the signal generating apparatus comprises:
• a pattern generating section that generates waveform data of the pattern signal to be generated;
• a timing generating section that generates timing signals in accordance with an expected pattern cycle time of the pattern signal;
• a timing control section that receives the waveform data output from the pattern generating section, and controls output timings of the timing signals to be output from the timing generating section, in accordance with the waveform data;
• and
• a waveform shaping section that generates the pattern signal corresponding to data values of the waveform data output from the pattern generating section, in accordance with the timing signals output from the timing generating section.

A test apparatus for testing a device under test, comprising:

• a signal generating apparatus that inputs a pattern signal into the device under test;
• a signal detecting apparatus that detects an output signal output from the device under test;
• and
• a judging section that judges whether the device under test is acceptable based on the output signal detected by the signal detecting apparatus, wherein
• the signal detecting apparatus comprises:
• a first comparing section that detects a logic value of the output signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the output signal in accordance with a second timing signal having a different phase from the first timing signal;
• a selection control section that detects a waveform pattern of the output signal based on one of (i) the logic value of the output signal detected by the first comparing section and (ii) the logic value of the output signal detected by the second comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the output signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the output signal, and outputs the selected logic value.

A test apparatus for testing a device under test, comprising:

• a signal generating apparatus that inputs a pattern signal into the device under test;
• a signal detecting apparatus that detects an output signal output from the device under test;
• and
• a judging section that judges whether the device under test is acceptable based on the output signal detected by the signal detecting apparatus, wherein
• the signal detecting apparatus comprises:
• a first comparing section that detects a logic value of the output signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the output signal in accordance with a second timing signal having a different phase from the first timing signal;
• a third comparing section that detects a logic value of the output signal at a substantially middle timing of each cycle of the output signal;
• a selection control section that detects a waveform pattern of the output signal based on the logic value of the output signal detected by the third comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the output signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the output signal, and outputs the selected logic value.

An electronic device comprising:

• a circuit under test;
• and
• a test circuit that tests the circuit under test, the test circuit comprising:
• a signal generating circuit that inputs a pattern signal into the circuit under test;
• a signal detecting circuit that detects an output signal output from the circuit under test;
• and
• a judging section that judges whether the circuit under test is acceptable based on the output signal detected by the signal detecting circuit, wherein
• the signal detecting circuit comprises:
• a first comparing section that detects a logic value of the output signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the output signal in accordance with a second timing signal having a different phase from the first timing signal;
• a selection control section that detects a waveform pattern of the output signal based on one of (i) the logic value of the output signal detected by the first comparing section and (ii) the logic value of the output signal detected by the second comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the output signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the output signal, and outputs the selected logic value.

An electronic device comprising:

• a circuit under test;
• and
• a test circuit that tests the circuit under test,
• the test circuit comprising:
• a signal generating circuit that inputs a pattern signal into the circuit under test;
• a signal detecting circuit that detects an output signal output from the circuit under test;
• and
• a judging section that judges whether the circuit under test is acceptable based on the output signal detected by the signal detecting circuit, wherein
• the signal detecting circuit comprises:
• a first comparing section that detects a logic value of the output signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the output signal in accordance with a second timing signal having a different phase from the first timing signal;
• a third comparing section that detects a logic value of the output signal at a substantially middle timing of each cycle of the output signal;
• a selection control section that detects a waveform pattern of the output signal based on the logic value of the output signal detected by the third comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the output signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the output signal, and outputs the selected logic value.

A program causing an information processing apparatus to function as a signal output apparatus that outputs a pattern signal, the program causing the information processing apparatus to function as:

• a pattern generating section that generates waveform data of the pattern signal to be generated;
• a timing generating section that generates timing signals in accordance with an expected pattern cycle time of the pattern signal;
• a timing control section that receives the waveform data output from the pattern generating section, and controls output timings of the timing signals to be output from the timing generating section, in accordance with the waveform data;
• and
• a waveform shaping section that generates the pattern signal corresponding to data values of the waveform data output from the pattern generating section, in accordance with the timing signals output from the timing generating section.

A program causing an information processing apparatus to function as a signal detecting apparatus that detects a pattern signal input thereto, the program causing the information processing apparatus to function as:

• a first comparing section that detects a logic value of the pattern signal in accordance with a first timing signal having a predetermined cycle time;
• a second comparing section that detects a logic value of the pattern signal in accordance with a second timing signal having a different phase from the first timing signal;
• a selection control section that detects a waveform pattern of the pattern signal based on one of (i) the logic value of the pattern signal detected by the first comparing section and (ii) the logic value of the pattern signal detected by the second comparing section, and uses the waveform pattern to judge which one of the logic value detected by the first comparing section and the logic value detected by the second comparing section is to be selected as a data value of each cycle of the pattern signal;
• and
• a selecting section that selects one of the logic value output from the first comparing section and the logic value output from the second comparing section based on the judgment made by the selection control section for each cycle of the pattern signal, and outputs the selected logic value.