Semiconductor integrated circuit device

A semiconductor integrated circuit device comprising:

• a plurality of memory cell arrays arranged with a plurality of electrically reprogrammable memory cells;
• a control circuit which controls the operations of internal circuits;
• a data program/read circuit which transfers programming data to said plurality of memory cell arrays and which reads out data from said plurality of memory cell arrays;
• a data input/output circuit which transfers externally input data to said data program/read circuit and which externally outputs data transferred from said data program/read circuit;
• an address register which includes an internal selection circuit which is connected with said control circuit, said address register transferring externally input address data to said data program/read circuit;
• a signal generation instruction circuit which receives an externally provided command and instructs said control circuit so that a predetermined internal control signal is generated;
• and
• a latch circuit, a plurality of which are arranged corresponding to a number of bits of externally provided test parameter data, one end of said latch circuit being connected to said control circuit, said data input/output circuit and said address register and the other end of said latch circuit being connected to said data program/read circuit, and said control circuit receiving an instruction from said signal generation instruction circuit and generating an internal control signal which addresses said plurality of latch circuits corresponding to predetermined bits of said test parameter data and transferring said internal control signal to said selection circuit, and said selection circuit receiving said internal control signal and controlling a test so that a fixed value data of said test parameter data is changed.

A test method of a semiconductor integrated circuit device comprising:

• performing a test by inputting first test parameter data for a predetermined address of a semiconductor integrated circuit device to said a semiconductor integrated circuit device from a test device;
• receiving a test result of said test using said first test parameter data for said address transferred from said semiconductor integrated circuit device and judging in said test device whether a trimming process for each bit of said first test parameter data for said address is complete or not;
• performing a test by inputting a predetermined command and second test parameter data to said semiconductor integrated circuit device from said test device;
• receiving a test result of said test using said second test parameter data for said address transferred from said semiconductor integrated circuit device and judging in said test device whether said test using said second test parameter data for said address is complete or not and outputting a first judgment result;
• judging in said test device whether said address is a final address or not and outputting a second judgment result;
• and
• repeating said tests until each of said judgments results ends in a pass.