Multiphase Clocking Systems with Ring Bus Architecture

A method implemented in a system having a plurality of digital circuit components coupled to corresponding latches in a ring bus, the method comprising:

• generating a plurality of clock signals, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals;
• providing each of the clock signals to a different one of the digital circuit components;
• and
• clocking data into the latch corresponding to one of the digital circuit components based on the clock signal provided to the digital circuit component.

A multiprocessor comprising:

• a plurality of processor cores;
• a timing system which is configured
• to generate a plurality of clock signals at a single clock frequency, wherein each of the clock signals is phase-shifted with respect to the remainder of the clock signals, and
• to provide each of the clock signals to a different one of the processor cores;
• and
• a bidirectional ring bus which includes a plurality of latches, wherein each of the latches is coupled to a corresponding one of the processor cores to enable the processor cores to transmit and receive data on the bus, wherein each of the latches is clocked by the clock signal provided to the processor core associated with the latch, and wherein data is transferred between consecutive ones of the latches in an amount of time that is less than a clock period of the clock signals.