Phase comparator and regulation circuit

A phase comparator for use in clock data recovery means for performing phase regulation and receiving data by using 2N phases of clock signals whose period is NT (N is an integer greater than or equal to 1) and whose phase difference is 0.5 T in data communication where a data rate is 1/T bps, the phase comparator comprising:

• N comparison period detection means each for determining whether it is within an mth comparison period, which is defined as a period between a rising edge of a first clock signal and a rising edge of a second clock signal, to output the determination result as an mth comparison enable signal, wherein the first clock signal is the (2m−2)th-phase (2m−2 is a remainder of division by 2N when it is greater than or equal to 0 and is obtained as 2m+2N−2 when it is a negative number) clock signal among the 2N phases of clock signals, and the second clock signal is the 2mth-phase (m is an integer greater than or equal to 0 and less than or equal to N−1) clock signal;
• and
• N phase difference detection means each for receiving the mth comparison enable signal, the data and a reference clock to output information on a phase difference between the reference clock and the data when the mth comparison enable signal is active, wherein the reference clock is the (2m−1)th-phase (2m−1 is a remainder of division by 2N when it is greater than or equal to 0 and is obtained as 2m+2N−1) clock signal.