Process for the vertical interconnection of 3d electronic modules by vias

Process for the vertical interconnection of n 3D electronic modules, n being an integer greater than 1, a module comprising a stack of K electronic wafer levels, a wafer level i, i varying from 1 to K, comprising at least one electronic component, the K wafer levels being electrically connected together by conductors lying along the direction of the stack, and comprises a first step consisting, for each wafer level i, of:

• A) a step of fabricating a batch of n wafer levels, a wafer level comprising at least n geometric features bounded by dicing lines, each feature being provided with at least one electronic component surrounded by insulating resin and connected to electrical connection pads, the pads being connected to electrical connection tracks deposited on a dielectric layer, wherein each track extends as far as an electrode interconnecting the tracks and located on the dicing lines, and comprises a curved segment placed between two straight segments, the curved segment defining a zone that surrounds a location intended to form a via, this zone being placed between the connection pad and the track interconnection electrode, and a second step consisting in:
• B) stacking and assembling the K wafer levels obtained after the first step so as to superpose said zones approximately one on top of another;
• C) drilling vias in the resin along the direction of the stack and over the entire thickness of the latter plumb with the locations of the vias, the cross section of the vias being such that, for each wafer level, the straight segments are flush with the vias but not with the curved segments;
• D) metallizing the wall of the vias by electrolytic growth;
• and
• E) cutting the stack along the dicing lines, the width of the cuts being greater than that of the electrode, so as to obtain the n 3D electronic modules.