Programmable linear receiver for digital data clock signals

A receiver architecture for a computer processor, the receiver architecture comprising:

• a plurality of data (DQ) receivers, each comprising a respective programmable linear receiver portion that receives a respective DQ signal and a reference voltage, compares the DQ signal to the reference voltage, and generates a differential output signal in response to the comparison;
• a data strobe (DQS) receiver coupled to each of the DQ receivers, the DQS receiver being configured to receive a differential DQS input signal for the DQ receivers, and to generate a differential DQS output signal in response to the differential DQS input signal;
• a delay locked loop coupled to the DQS receiver, the delay locked loop being configured to receive the differential DQS output signal, and to generate therefrom a clock signal for clocking the DQ receivers;
• and
• a programming architecture coupled to the DQ receivers and to the DQS receiver, the programming architecture being configured to set operating characteristics of the DQ receivers and the DQS receiver;
• wherein
• the DQS receiver and the delay locked loop are cooperatively configured to generate the clock signal with transition edge timing such that the clock signal can be used to sample the differential output signals of the DQ receivers at a sampling time when all of the differential output signals are well-settled.

A method of operating a receiver architecture for a computer processor, the method comprising:

• programming a differential data strobe (DQS) receiver to achieve a programmable voltage swing;
• receiving a DQS signal and a plurality of single-ended data (DQ) signals from a memory device, the differential DQS signal and the DQ signals originating from the memory device in a substantially edge-aligned manner;
• processing each DQ signal with a respective DQ receiver to compare the DQ signal to a reference voltage, and to generate a differential output signal in response to the comparison;
• processing the differential DQS signal with the DQS receiver to generate a differential DQS output signal having the programmable voltage swing;
• deriving a clock signal from the differential DQS output signal;
• and
• sampling the differential output signals of the DQ receivers with a transition edge of the clock signal at a sampling time when all of the differential output signals are well-settled.